1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly, to a semiconductor device having a trench isolation region and a manufacturing method therefor.
2. Description of the Related Art
In a semiconductor integrated circuit, a LOCOS (LOCal Oxidation of Silicon) process in which a semiconductor substrate is oxidized using a nitride as a mask is used for isolating devices. Since an isolation layer formed by the LOCOS process is a thermal oxide, it is a densified film but ensures a low level of integration. According to the recent high integration of a semiconductor integrated circuit, a shallow trench isolation technology is widely used for overcoming the limit of integration levels of devices in case of using isolation layers formed by the LOCOS process. Hereinbelow, a conventional semiconductor device of the prior art having a trench isolation region will be described with reference to FIG. 1A-1D.
FIG. 1A is a layout diagram of an active region pattern 102 and a gate electrode pattern 162. FIG. 1B is a cross-sectional view taken along A-A' direction of FIG. 1A. Referring to FIG. 1B, an isolation region and an active region are formed on a semiconductor substrate 100. Source/drain 150, a gate insulation layer 160, a gate electrode 162 and a gate spacer 164 are formed in the active region. Also, a side wall insulation layer 120 and an insulator burial layer 130 are formed in the trench isolation area.
FIG. 1C is a cross-sectional view taken along B-B' direction of FIG. 1A. Referring to FIG. 1C, the side wall insulation layer 120 is formed at the side walls and on the bottom of a trench, and the insulator burial layer 130 for filling the trench is formed. Also, the gate electrode 162 is formed on the active region. A fabrication process of the semiconductor device will be described briefly. First, a buffer layer (not shown) and a photosensitive layer (not shown) are formed on the semiconductor substrate 100 and patterned. A non-active region is etched using the patterned buffer layer and the patterned photosensitive layer as a mask to form a trench. Next, the side wall insulation layer 120 is formed at the side walls and on the bottom of the trench and then the insulator burial layer 130 is formed. Next, a wet etch process is performed for removing the buffer layer. Here, since the buffer layer is formed by thermally oxidizing the semiconductor substrate 100, the buffer layer bonding structure is densified film. However, the insulator burial layer 130 for burying the trench is an oxide formed by performing a chemical vapor deposition process at a low temperature. Thus, the insulator burial layer 130 is less denser than that of the buffer layer. As a result, when performing the wet etch process for removing the buffer layer, the insulator burial layer 130 is etched away 2-5 times faster than the buffer layer. Also, since edges of the insulator burial layer 130 adjacent to the active region are simultaneously etched at the side walls and on the upper surface thereof, the edges are etched away more than the central portion. Thus, as indicated by a region C in FIG. 1C, the edges of the insulator burial layer 130 are etched more deeply than the surface of the active region so that an undesired groove is formed. FIG. 1D is an enlarged cross-sectional view of the region C shown in FIG. 1C. The gate electrode 162 is formed on the active region and at the side walls of the active region where the groove is formed.
Now, the operation of the device will be described. If power greater than a threshold voltage is applied to the gate electrode 162, a channel is formed in the active region below the gate insulation layer 160, which causes current to flow from the source to the drain. However, as shown in FIG. 1D, if the undesired groove is formed at the edges of the insulator burial layer 130, the gate electrode 162 is formed on top of and at the side walls of the active region. As a result, if a voltage is applied to the gate electrode 162, only a vertical electric field x ranging toward the upper surface of the active region is induced in the central portion of the active region. However, in the edges of the active region, both a vertical electric field y ranging toward the upper surface of the active region and a side wall electric field z ranging toward the side wall of the active region of the gate electrode 162 are induced. Thus, even if a voltage lower than a threshold voltage is applied to the gate electrode 162, a stronger electric field is induced in the edge portion of the active region than in the central portion. As a result, even if a voltage lower than the threshold voltage is applied to the gate electrode 162, a channel is induced in the edge portion of the active region, so that unwanted current flows from the source to the drain.
To solve the problem, that is, the device is turned on at the voltage lower than the threshold voltage, the formation of the groove in the edges of the insulator burial layer 130 must be suppressed. To this end, a wet etch time is minimized in the conventional art. However, in this case, it is difficult to keep a constant concentration of an etching solution used in the wet etch process, thereby disabling to obtain the same resultant structure.